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Scaling of 32nm low power SRAM with high-K metal gate
, Yang H.S., Wong R., Hasumi R., Gao Y., Kim N.S., Lee D.H., Badrudduza S., Ostermayr M., Kang H.Show More
Published in IEEE
This paper describes SRAM scaling for 32nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 μm 2 and 0.124μm 2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T invinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 μm 2 cell to meet low power application requirements.
About the journal
JournalData powered by TypesetTechnical Digest - International Electron Devices Meeting, IEDM
PublisherData powered by TypesetIEEE
Open AccessNo