Logic minimization is an important aspect of the digital Computer Aided Design flows of both Application Specific Integrated Circuits and Field Programmable Gate Arrays. Peephole optimization is one of the effective logic minimization technique employed in design of digital circuits. This paper presents a novel automated peephole optimization based approach for logic minimization that interlaces commercially available ASIC-based and FPGA-based synthesis tools in an alternating fashion. Experimenting the technique on standard benchmark circuits resulted in a logic reduction of upto 59.71% and 73.40%; delay reduction of upto 36.64% and 57.78%; and, power reduction of upto 54.12% and 57.14% when compared with the output generated by current commercial state-of-the-art ASIC and FPGA synthesis tools respectively. Importantly, this technique can be adopted by design houses at no extra cost. Using the addition operation as a case study the paper also demonstrates how to use the proposed methodology to automatically design arithmetic circuits that meet different area and performance budgets. Copyright © 2014 American Scientific Publishers