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PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology
, Song L., Liang Y., Onoda H., Lai C.W., Wallner T.A., Pofelski A., Gruensfelder C., Josse E., Okawa T.Show More
Published in IEEE
2012
Abstract
The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process. © 2012 IEEE.
About the journal
JournalData powered by TypesetInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
PublisherData powered by TypesetIEEE
ISSN19308868
Open AccessNo