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New layout dependency in high-k/metal gate MOSFETs
, Hamaguchi M., Jaeger D., Nishimura H., Li W., Na M.-H., Bernicot C., Liang J., Stahrenberg K., Kim K.Show More
Published in IEEE
We report a new N/PFET Gate Patterning Boundary Proximity layout dependent effect in high-k dielectric/Metal Gate (HK/MG) MOSFETs which causes anomalous threshold voltage (Vt) modulation for the first time. We investigated the mechanism by using special test structures and process optimizations to suppress this layout dependency. Finally, we achieved the best over all process optimization which makes it possible to suppress layout dependency without degrading FET performance/yield/reliability. © 2011 IEEE.
About the journal
JournalData powered by TypesetTechnical Digest - International Electron Devices Meeting, IEDM
PublisherData powered by TypesetIEEE
Open AccessNo