The advantages of multiple gate MOSFETs (MuGFETs) are discussed. The interesting concept of operation of a fully depleted single gate SOI MOSFET as a virtual double gate MOSFET is highlighted. Also, the advantages of lower gate leakage current and short-channel effects in MuGFETs are discussed in detail. © 2007 IEEE.

Amitava Dasgupta

Department of Electrical Engineering

electric conductivity

Electron beam lithography

Field effect transistors

Leakage currents

Semiconductor device manufacture

Semiconductor device models

Semiconductor devices

Semiconductor materials

Semiconductor switches

CMOS

CONCEPT OF OPERATIONS

DOUBLE GATE MOSFET

FinFET

FULLY DEPLETED

Fully depleted silicon-on-insulator (FDSOI)

GATE-LEAKAGE CURRENTS

MOSFETs

Multiple gate MOSFETs

MULTIPLE-GATE

Short-channel effects

SINGLE GATE

SOI-MOSFET

MOSFET devices

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Multiple gate MOSFETs: The road to the future

Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD

In this paper, we show that when single gate SOI MOSFETs are biased at a particular ideal back gate voltage, the front and back channels can be turned ON and OFF simultaneously using the front gate voltage, thereby enhancing the current drive of the device. It is shown by analytical models as well as 2-D numerical simulation that both maximum transconductance and minimum subthreshold slope are obtained for this ideal back gate bias. Subsequently, n-channel and p-channel MOSFETs are designed for a conventional SOI CMOS process, where both the front and back channels of these devices turn ON and OFF simultaneously resulting in enhanced current drive and superior performance. The design has been carried out with the help of analytical formulation and verified using the 2-D Device Simulator MEDICI. © 2006 Elsevier Ltd. All rights reserved.

Solid-State Electronics

Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

Quantum confinement in the ultra-thin silicon film of Double gate SOI MOSFETs affects the gate current (IG). In this work, a systematic study on IG in such devices for various high-κ/stacked gate dielectric material combinations with Equivalent Oxide thickness in the range of 1 to 2 nm has been carried out using a simulator developed for this purpose. The lower IG in DG devices compared to bulk devices is attributed to reduced vertical electric field and quantum confinement effects. The amount of improvement is affected by the body thickness and the thickness of the gate dielectric. With higher value of κ, the reduction in IG is even more pronounced. The gate dielectric can thus be more aggressively scaled with DG MOSFETs than with bulk-MOSFETs. It is found from our studies that Al 2O3 is a better interfacial layer than SiO2 and La2O3 is the most promising dielectric material to sustain scaling for the next decade. © 2005 Elsevier B.V. All rights reserved.

Thin Solid Films

Study of gate leakage current in symmetric double gate MOSFETs with high-κ/stacked dielectrics

A threshold voltage model for mesa-isolated fully depleted silicon-on-insulator (FDSOI) MOSFETs, based on the analytical solution of three-dimensional (3-D) Poisson's equation is presented for the first time in this paper. The separation of variables technique is used to solve the 3-D Poisson's equation analytically with appropriate boundary conditions. Simple and accurate analytical expressions for the threshold voltage of the front and the back gate are derived. The model is able to predict short channel as well as narrow width effects in mesa-isolated FDSOI MOSFETs. The model is validated by comparing with the experimental results as well as with the numerical results available in the literature. © 2004 IEEE.

IEEE Transactions on Electron Devices

Threshold voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution OF 3-D poisson's equation

2009 International SoC Design Conference (ISOCC)

A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS)

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

Journal	Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD
Open Access	No