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Modeling of gate-induced drain leakage mechanisms in silicon-germanium channel pFET
Published in Institute of Electrical and Electronics Engineers Inc.
2014
Abstract
Silicon-Germanium is used as an alternative channel material for pFET in high-k metal gate-first technologies for 32 nm and beyond. However, gate-induced drain leakage (GIDL) is significant at nominal bias due to band-to-band tunneling (BTBT) at the gate-to-drain overlap surface and gate sidewall junctions. In this work, the results of numerical simulation are compared with experimental results for SiGe channel pFET and the calibrated models are used to describe the GIDL mechanisms in the dominant region for various drain and gate bias voltages. The simulation results correspond well with the experimental data, illustrating that the models presented in this paper can be used to describe the GIDL mechanisms and help to reduce the overall leakage budget for low-leakage, high-threshold voltage (HVT) device designs. © 2014 IEEE.
Concepts (17)
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    Bias voltage
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    Budget control
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    Computer aided design
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    Computer simulation
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    ELECTRONIC DESIGN AUTOMATION
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    Germanium
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    Numerical models
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    Silicon
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    Silicon alloys
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    Threshold voltage
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    Band to band tunneling
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    GATE INDUCED DRAIN LEAKAGES
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    High-k metal gates
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    Silicon germanium
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    TECHNOLOGY COMPUTER AIDED DESIGN
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    Trap assisted tunneling
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    Bicmos technology