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MemMap-pd: Performance driven technology mapping algorithm for FPGAs with embedded memory arrays
B. Jayaram,
Published in
2004
Volume: 18
   
Pages: 2081 - 2088
Abstract
Modern day Field Programmable Gate Arrays (FPGA) include in addition to Look-up Tables, reasonably big configurable Embedded Memory Blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, with depth minimization as the main objective along with area minimization in terms of the number of LUTs used. Depth minimization is an important goal while mapping performance driven circuits. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, leads to upto 14% reduction in depth compared with the DAG-Map, along with comparable reduction in area.
About the journal
JournalProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)
Open AccessNo
Concepts (12)
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    Algorithms
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    ARRAYS
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    Computer architecture
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    Embedded systems
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    Microprocessor chips
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    Networks (circuits)
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    Problem solving
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    BENCHMARK CIRCUITS
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    EMBEDDED MEMORY ARRAYS
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    EMBEDDED MEMORY BLOCKS (EMB)
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    ON-CHIP MEMORY
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    Field programmable gate arrays