Header menu link for other important links
X
Karna: A gate-sizing based security aware EDA flow for improved power side-channel attack protection
Published in Institute of Electrical and Electronics Engineers Inc.
2019
Volume: 2019-November
   
Abstract
Power side-channel attacks pose a serious threat to the security of embedded devices. Most available countermeasures have significant overheads resulting in the application not meeting its requirements of low-power, high-performance and small area. We propose an algorithm called Karna11Karna, much like Achilles from Greek mythology, was born with a shield that protected him from attacks. Similarly, Our proposed scheme, Karna protects the design from power side-channel attacks in the manufacturing phase or in other words the chip is manufactured(born) with a shield. that can be incorporated in the Electronic Design Automation (EDA) flow, in order to significantly improve the side-channel security of the device, without impacting the other device characteristics. Karna does not add additional logic but rather achieves this by first identifying vulnerable gates in the design and then reconfiguring these gates to increase side-channel resistance. Unlike contemporary works, Karna does not require any specialized gate library but uses the gates available in the standard cell library. We integrate Karna into the Synopsys Design Compiler and demonstrate its efficacy at reducing side-channel leakage in implementations of AES, PRESENT and Simon block ciphers, synthesized for a 28nm technology node. An interesting observation is that Karna only uses the available space around the gates to perform this optimization and does not incur any additional area overheads. We showcase the side-channel resistance of these optimized designs using a Differential Power Analysis attack. Our proposed approach is able to reduce the power side-channel of the designs while incurring no penalty in delay, power and gate-count. © 2019 IEEE.
About the journal
JournalData powered by TypesetIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN10923152
Open AccessNo
Concepts (12)
  •  related image
    ELECTRONIC DESIGN AUTOMATION
  •  related image
    Gates (transistor)
  •  related image
    RADAR COUNTERMEASURES
  •  related image
    ADDITIONAL LOGIC
  •  related image
    DESIGN COMPILER
  •  related image
    Device characteristics
  •  related image
    DIFFERENTIAL POWER ANALYSIS ATTACK
  •  related image
    EMBEDDED DEVICE
  •  related image
    MANUFACTURING PHASE
  •  related image
    Optimized designs
  •  related image
    Technology nodes
  •  related image
    Side channel attack