Finite-impulse-response (FIR) feedback was originally introduced as a way to address the problem of loopfilter nonlinearity and clock jitter in continuous-time delta-sigma modulators. It turns out that FIR feedback has other benefits - it reduces the effect of the quantizer's data-dependent jitter and enables the use of chopping 'for free'. It is an architectural technique that combines the benefits of single-bit and multibit operation, and has proven itself to be robust and scalable, applicable to ΔΣ data converters targeting a variety of specifications, and across process nodes. This paper reviews the key challenges encountered in the design of high performance delta-sigma data converters, and describes the role of FIR feedback in addressing these challenges. The prospect of using FIR feedback to achieve wide bandwidths is examined, and promising directions are reviewed. © 2018 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

FIR filters

Impulse response

Integrated circuits

Jitter

MODULATORS

Continuous-time

DATA CONVERTER

DATA-DEPENDENT JITTER

DELTA SIGMA MODULATOR

DELTA-SIGMA CONVERTERS

FINITE IMPULSE RESPONSES (FIR)

MULTIBIT OPERATIONS

Wide bandwidth

Continuous time systems

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IIT Madras

Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters

2018 IEEE Custom Integrated Circuits Conference, CICC 2018

The use of a single-bit quantizer in a wideband CT Δ Σ M is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CT Δ Σ Ms are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform results in increased power dissipation. The use of a finite impulse response (FIR) feedback DAC is a power efficient way of addressing the challenges above. However, even this technique runs into difficulties at multi-GHz clock rates. This paper introduces the idea of time-interleaved (TI) FIR feedback to enhance the performance of a conventional FIR DAC. A single-bit CT Δ Σ M that uses a 2 × TI-FIR DAC achieves 67.6/68.8/76 dB SNDR/SNR/DR in a 60 MHz bandwidth. Designed in a low leakage 65 nm CMOS process, the modulator operates at 6 GHz and occupies only 0.07 mm2. Its Walden Figure of Merit is 56.5 fJ/lvl. © 2017 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback

Chopping is a commonly used technique to eliminate flicker noise in amplifiers. We investigate the use of chopping in the input integrator of a continuous-time oversampling (Δ Σ) converter. Unlike an amplifier, the integrator in a continuous-time delta-sigma modulator is subject to out-of-band signals that are several orders of magnitude higher than the (desired) in-band component. This necessitates a careful analysis of frequency translation effects in a chopped integrator. This paper treats the chopped integrator as a linear periodically time-varying system, and exploits the adjoint (inter-reciprocal) network concept to simplify the analysis of aliasing effects in such an integrator. Simulation results that confirm the theory are given. © 2017 IEEE.

Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT ΔΣ M is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- RC integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT ΔΣM, which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 μW from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a 1/f noise corner of about 3 Hz when chopped at fs/24. © 1966-2012 IEEE.

IEEE Journal of Solid-State Circuits

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping

Many industrial applications require high-resolution ADCs whose low-frequency performance is important. CTDSMs are attractive due to their implicit antialiasing and resistive inputs. However, their low-frequency precision is degraded by flicker noise. The loop filter of such modulators is usually realized using active-RC techniques, and the CTDSMs' 1/f noise is mostly due to the input stage of the 1st OTA. Using large input devices to reduce 1/f noise greatly increases area occupied by the input stage, and degrades linearity due to the increased parasitic capacitance at the OTA virtual ground. © 2016 IEEE.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ?SM achieving &lt;10Hz 1/f noise corner without chopping artifacts

We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step. © 2016 IEEE.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback

Journal	Data powered by Typeset2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open Access	No