Of late, the fast Hartley transform (FHT) has attracted considerable research interest as an alternative tool to the fast Fourier transform (FFT). In this paper, efficient implementation of the FHT on different DSP processors is considered. Instead of counting the required arithmetic operations, the necessary number of instruction cycles for an implementation of FHT is used as a measure. Also, different scaling schemes, which are available in the literature, have been considered to increase the signal-to-noise ratio (SNR) of the algorithm. Finally, the details of the programs on ADSP2101, TMS320C25 and TMS320C30 have been presented.

K. M.Muraleedhara Prabhu

Ravi Shanmuga Sundaram

Algorithms

Digital signal processing

Mathematical transformations

Signal to noise ratio

FAST HARTLEY TRANSFORM

INSTRUCTION CYCLES

Microprocessor chips

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Fast Hartley transform implementation on DSP chips

Microprocessors and Microsystems

The fast Hartley transform (FHT) is emerging as an alternative to the more popular fast Fourier transform (FFT) in the processing of real signals. In this paper, a fixed-point error analysis has been carried out. The basic differences between the FFT and FHT flowcharts from the point of view of error analysis are first discussed. A suitable scaling model is chosen for the FHT and the average output signal-to-noise ratio is calculated both for decimation-in-frequency and decimation-in-time cases. The results are then compared with the FFT error-analysis results. © 1990.

Signal Processing

Fixed-point error analysis of fast Hartley transform

Real-Time Digital Signal Processing

Introduction to TMS320C55x Digital Signal Processor

IEEE Transactions on Signal Processing

Computing pseudo-Wigner distribution by the fast Hartley transform

IEEE Transactions on Acoustics, Speech, and Signal Processing

Real-valued fast Fourier transform algorithms

On computing the discrete Hartley transform

Journal	Data powered by TypesetMicroprocessors and Microsystems
Publisher	Data powered by TypesetElsevier
ISSN	01419331
Open Access	No