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Fast Hartley transform implementation on DSP chips
K. M.Muraleedhara Prabhu, Ravi Shanmuga Sundaram
Published in Elsevier
1996
Volume: 20
   
Issue: 4
Pages: 233 - 240A
Abstract
Of late, the fast Hartley transform (FHT) has attracted considerable research interest as an alternative tool to the fast Fourier transform (FFT). In this paper, efficient implementation of the FHT on different DSP processors is considered. Instead of counting the required arithmetic operations, the necessary number of instruction cycles for an implementation of FHT is used as a measure. Also, different scaling schemes, which are available in the literature, have been considered to increase the signal-to-noise ratio (SNR) of the algorithm. Finally, the details of the programs on ADSP2101, TMS320C25 and TMS320C30 have been presented.
About the journal
JournalData powered by TypesetMicroprocessors and Microsystems
PublisherData powered by TypesetElsevier
ISSN01419331
Open AccessNo
Concepts (7)
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    Algorithms
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    Digital signal processing
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    Mathematical transformations
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    Signal to noise ratio
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    FAST HARTLEY TRANSFORM
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    INSTRUCTION CYCLES
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    Microprocessor chips