On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but the propagation delay is data dependent and data is application dependent. Different applications may have different data behavior. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give different performance results. In this paper, by exploiting data behavior, we propose two on-chip delay minimization techniques, namely, data packing and data permutation. We validate our techniques by focusing on the L1 cache address/data buses using SPEC2000 CINT benchmarks. We show that, in the address bus case, the data packing and data permutation techniques achieve more than 2.3X and 1.6X speedup, respectively, over the unencoded bus, whereas in the case of data bus, both these techniques achieve more than 1.5X and 1.4X speedup, respectively. For a 32-bit bus, both data packing and data permutation techniques require 38 and 34 wires, respectively. Copyright 2007 ACM.