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Dynamic coding technique for low-power data bus
, Vadali Srinivasa Murty,
Published in IEEE Computer Society
2003
Volume: 2003-January
   
Pages: 252 - 253
Abstract
Designing chips for lower power applications is one of the most important challenges faced by the VLSI designers. Since the power consumed by I/O pins of a CPU is a significant source of power consumption, work has been done on developing encoding schemes for reducing switching activity on external buses. In this paper we propose a new coding technique, namely, the Dynamic Coding Scheme, for low-power data bus. Our method considers two logical groupings of the bus lines, each being a permutation of the bus lines, and dynamically selects that grouping which yields the minimum number of transitions. © 2003 IEEE.
About the journal
JournalData powered by TypesetProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
PublisherData powered by TypesetIEEE Computer Society
ISSN21593469
Open AccessNo
Concepts (19)
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    Application programs
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    Bus terminals
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    Capacitance
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    Codes (symbols)
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    Computer science
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    Energy utilization
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    Hamming distance
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    Networks (circuits)
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    SYSTEM BUSES
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    Vlsi circuits
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    Application softwares
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    Coding techniques
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    DH-HEMTS
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    Encoding schemes
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    PINS
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    Power applications
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    POWER ENGINEERING AND ENERGIES
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    Switching activities
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    Buses