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Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters with Low In-Band Noise Spectral Density
, Theertham R., Koottala P., Billa S.
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 55
Issue: 9
Pages: 2429 - 2442
We present design considerations for CT Δ Σ Ms that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT Δ Σ M targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB. © 1966-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Journal of Solid-State Circuits
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo