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Design and implementation of High Performance Visual Stimulator for Brain Computer Interfaces
Published in IEEE

An algorithm for implementing visual stimulators on generic computers has been developed for brain computer interfaces (BCIs). It uses the hardware counter present in these systems to derive accurate timing. Simultaneous display of 20 patterns (e.g. 3times3 checkerboards) modulated at different frequencies is possible. The pattern used for stimulating the steady state visual evoked potential (SSVEP) can be changed with ease. The stimulators are evaluated using software counters. High accuracy (less than 0.73% error) and precision (0.1% coefficient of variation) is recorded for 20 patterns set with frequencies between 6 Hz and 15 Hz

About the journal
JournalData powered by Typeset2005 IEEE Engineering in Medicine and Biology 27th Annual Conference
PublisherData powered by TypesetIEEE
Open AccessNo