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Delay and peak power minimization for on-chip buses using temporal redundancy
Published in
2006
Volume: 2006
   
Pages: 119 - 122
Abstract
In this paper, we propose a novel temporal redundancy based encoding technique for delay and peak power minimization. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks for 90nm and 65nm technologies. The experimental results show that our approach is very effective in reducing the peak power. From the delay perspective, our approach reduces the delay by at least 11% (4%) in the address (data) buses compared to the data transmission without encoding. Copyright 2006 ACM.
About the journal
JournalProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Open AccessNo
Concepts (9)
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    Chip scale packages
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    Crosstalk
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    Delay circuits
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    Encoding (symbols)
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    Nanotechnology
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    Data transmission
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    PEAK POWER MINIMIZATION
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    Temporal redundancy
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    Busbars