The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves finding input vectors that cause maximum dynamic power dissipation (maximum toggles) in circuits. In this paper, an approach for power virus generation for both combinational and sequential circuits is presented. The basic intuition behind the approach is to use the 0- and 1- controllability measures of the gate outputs in the circuit to guide the D-Algorithm. The proposed technique was employed on the ISCAS'85 and ISCAS'89 circuits. The results of the above show a significant increase in power dissipation when compared to the best known existing techniques reported in the literature. © 2007 IEEE.

Veezhinathan Kamakoti

Department of Computer Science and Engineering

K. Najeeb

CMOS circuits

DYNAMIC POWER DISSIPATIONS

Extreme conditions

FANOUT FREE REGIONS

INPUT VECTORS

PEAK POWERS

Power dissipation

POWER VIRUS

PROBLEM INVOLVES

Automatic test pattern generation

Computer programming languages

Control theory

Controllability

Data compression

Digital integrated circuits

Electric power utilization

Embedded systems

Integrated circuits

Logic circuits

Networks (circuits)

Viruses

VLSI circuits

Digital circuits

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IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Controllability-driven Power Virus Generation for Digital Circuits

Proceedings of the IEEE International Conference on VLSI Design

Scan-based testing is crucial to ensuring correct functioning of chips. In this scheme, the scan and capture phases are interleaved. It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to high voltage droop on the power grid, ultimately resulting in false delay failures during at-speed test. This article proposes a new design-for-testability (DFT) scheme for launch-onshift (LOS) testing, which ensures that the combinational logic remains undisturbed between the interleaved capture phases, providing computer-aided-design (CAD) tools with extra search space for minimizing launchto-capture switching activity through test pattern ordering (TPO). We further propose a new TPO algorithm that keeps track of the don't cares during the ordering process, so that the don't care filling step after the ordering process yields a better reduction in launch-to-capture switching activity compared to any other technique in the literature. The proposed DFT-assisted technique, when applied to circuits in ITC99 benchmark suite, produces an average reduction of 17.68% in peak launch-to-capture switching activity (CSA) compared to the best known lowpower TPO technique. Even for circuits whose test cubes are not rich in don't care bits, the proposed technique produces an average reduction of 15% in peak CSA, while for the circuits with test cubes rich in don't care bits (≥75%), the average reduction is 24%. The proposed technique also reduces the average power dissipation (considering both scan cells and combinational logic) during the scan phase by about 43.5% on an average, compared to the adjacent filling technique. © 2015 ACM.

ACM Transactions on Design Automation of Electronic Systems

DFT assisted techniques for peak launch-to-capture power reduction during launch-on-shift at-speed testing

Power has becomes one of the crucial parameter while designing a SOC ICs. Power analysis of a circuit is important for reliability check, better design of power distribution network, packaging decisions and to solve power issues during test. High switching at a time demands high instantaneous current from power supply network. Which gates experience Vdd drop leading to increase in delay of the circuit. Power consumed by circuit is proportional to switching activity at gate outputs and capacitance associated with it. Most of the previous work consider switching activity over entire clock period, however this is very pessimistic approach. All gates do not switch at the same time because of associated delays, thus peak switching occurring at an instant of time should be considered. In this paper we formulate an Integer Linear Programming for computing maximum transitions in the circuit at any instant time as well as during entire clock period. This method identifies a vector pair which provides the highest activity in the circuit. The proposed method captures the impact of glitches occurring during signal propagation. Our analysis shows that the maximum 75% of total gates can switch at any time instant and the maximum 625% of total gates can switch during clock period. © 2016 IEEE.

2016 20th International Symposium on VLSI Design and Test, VDAT 2016

On determination of instantaneous peak and cycle peak switching using ILP

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs

Peak power estimation of VLSI circuits: new peak power measures

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Maximization of power dissipation in large CMOS circuits considering spurious transitions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Estimation of average switching activity in combinational logic circuits using symbolic simulation

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution

Controllability-driven power virus generation for digital circuits

Journal	Proceedings of the IEEE International Conference on VLSI Design
ISSN	10639667
Open Access	No