Header menu link for other important links
X
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER
Bodduna R., Ganesan V., Slpsk P., Veezhinathan K.,
Published in Institute of Electrical and Electronics Engineers Inc.
2020
Volume: 19
   
Issue: 1
Pages: 9 - 12
Abstract
Cache timing attacks are a serious threat to the security of computing systems. It permits sensitive information, such as cryptographic keys, to leak across virtual machines and even to remote servers. Encrypted Address Cache, proposed by CEASER - a best paper candidate at MICRO 2018 - is a promising countermeasure that stymies the timing channel by employing cryptography to randomize the cache address space. The author claims strong security guarantees by providing randomization both spatially (randomizing every address) and temporally (changing the encryption key periodically). In this letter, we point out a serious flaw in their encryption approach that undermines the proposed security guarantees. Specifically, we show that the proposed Low-Latency Block Cipher, used for encryption in CEASER, is composed of only linear functions which neutralizes the spatial and temporal randomization. Thus, we show that the complexity of a cache timing attack remains unaltered even with the presence of CEASER. Further, we compare the encryption overheads if CEASER is implemented with a stronger encryption algorithm. © 2002-2011 IEEE.
About the journal
JournalData powered by TypesetIEEE Computer Architecture Letters
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN15566056
Open AccessNo