CORDIC (coordinate rotation digital computer) is an iterative arithmetic algorithm for computing generalized vector rotation in the X-Y plane, without performing multiplications. For applications where the angle of rotation is known in advance, the angle recoding technique speeds up the execution of the CORDIC algorithm by reducing the total number of iterations. In this paper, a generalized systolic array architecture has been proposed for prime length DFT and DHT. The arithmetic units of this array use the angle recoding CORDIC (ARC) computation technique for vector rotation. One of the major advantages of this architecture is that two of the most frequently used algorithms, the DFT and the DHT, are computed with this array, using the same hardware. The array proposed here has much better computational efficiency when compared to any of the existing CORDIC-based systolic arrays. This has been achieved because of the tremendous reduction in the number of CORDIC iterations made possible by using the ARC-based arithmetic units. The proposed architecture satisfies the fundamental requirement for the VLSI implementation of systolic architectures.