Silicon-germanium is an alternative channel material for pMOS FETs at 32-nm node and beyond because of lower threshold voltage and higher channel mobility in high- k metal gate technology. However, gate-induced drain leakage (GIDL) is a major concern at low power technology nodes because of band-to-band and trap-assisted tunneling (TAT) due to reduced bandgap. Here, we have studied the GIDL dependence on temperature as well as drain and substrate bias. Experimental results and Technology computer-aided design (TCAD) simulations suggest that the mechanism responsible for GIDL during off state is mostly phonon-assisted band-to-band tunneling (BTBT) in the top SiGe layer near the drain surface and is further contributed by BTBT at the drain sidewall junction. Other GIDL mechanisms such as TAT at the extension/sidewall dominate for other drain, gate, and substrate bias voltages. © 1963-2012 IEEE.

Deleep R. Nair

Department of Electrical Engineering

Computer aided design

Band to band tunneling

Gate first

GATE-INDUCED DRAIN LEAKAGE

PFET

silicon germanium

Trap assisted tunneling

Silicon alloys

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET

IEEE Transactions on Electron Devices

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon-germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage (VT) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage (IOFF) variability and in the halo region at the drain sidewall for VT variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar I OFF random variability for scaled voltages. © 1963-2012 IEEE.

OFF-State Leakage and Performance Variations Associated with Germanium Preamorphization Implant in Silicon-Germanium Channel pFET

Variability in the transistor parameters play a significant role in CMOS scaling to nanometer feature sizes. New channel materials such as silicon-germanium for pFET at 32nm and beyond are useful because of higher mobility and lower threshold voltage. However, gate-induced drain leakage (GIDL) is dominant in the total leakage and the use of germanium (Ge) may introduce additional variability sources. In this work, pre-halo Ge pre-amorphization impant (PAI) effect on systematic and random variability of GIDL and its reduction is investigated. We report that the elimination of Ge PAI from the process flow reduces GIDL and the effect of systematic variations but increases the static random GIDL variations in planar transistors based on high-k metal gate technology. However, the random GIDL variation difference associated with Ge PAI may change for scaled supply voltages. © 2016 IEEE.

2016 3rd International Conference on Emerging Electronics, ICEE 2016

Analysis of systematic and random variation of gate-induced drain leakage in silicon-germanium channel pFET

Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias. © 2016 The Japan Society of Applied Physics.

Japanese Journal of Applied Physics

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

Silicon-germanium (SiGe) channel pMOSFET is considered as a replacement for silicon channel device for 32-nm node and beyond, because of its lower threshold voltage and higher channel mobility. Lower SiGe bandgap makes gate-induced drain leakage (GIDL) important for low leakage, high threshold voltage device designs. In this letter, the effect of prehalo/LDD Ge preamorphization implant (PAI) on GIDL and performance is investigated using experimental data and simulations. Results suggest that GIDL reduction of 40 % is achieved without Ge PAI and the total off-state leakage (I<inf>OFF</inf>) is reduced by ∼ 50 % with a slight reduction in drive current (I<inf>ON</inf>) and similar short-channel effects as compared with the case with PAI for same process conditions, which is not reported yet. The reduction in GIDL, and hence the improvement in I<inf>ON</inf>/I<inf>OFF</inf> ratio is because of elimination of end-of-range defects at the source/drain sidewall junction regions. It is also shown that a slight reduction in I<inf>ON</inf> in the absence of Ge PAI is because of a small increase in the extrinsic series resistance. © 2015 IEEE.

IEEE Electron Device Letters

Effect of germanium preamorphization implant on performance and gate-induced drain leakage in SiGe channel pFET

Silicon-Germanium is used as an alternative channel material for pFET in high-k metal gate-first technologies for 32 nm and beyond. However, gate-induced drain leakage (GIDL) is significant at nominal bias due to band-to-band tunneling (BTBT) at the gate-to-drain overlap surface and gate sidewall junctions. In this work, the results of numerical simulation are compared with experimental results for SiGe channel pFET and the calibrated models are used to describe the GIDL mechanisms in the dominant region for various drain and gate bias voltages. The simulation results correspond well with the experimental data, illustrating that the models presented in this paper can be used to describe the GIDL mechanisms and help to reduce the overall leakage budget for low-leakage, high-threshold voltage (HVT) device designs. © 2014 IEEE.

2014 IEEE 2nd International Conference on Emerging Electronics: Materials to Devices, ICEE 2014 - Conference Proceedings

Modeling of gate-induced drain leakage mechanisms in silicon-germanium channel pFET

Obesity Research – Open Journal

A Couple’s Personalized-Care Intervention for Weight-Loss and Diabetes based on DNA and Gut Biome Profiles: A Case Study

ECS Transactions

Defects, Junction Leakage and Electrical Performance of Ge pFET Devices

Properties of Min-Max Detectors

Journal of Applied Physics

Electric-field and temperature dependence of the activation energy associated with gate induced drain leakage

Journal of The Electrochemical Society

Analysis of the Temperature Dependence of Trap-Assisted Tunneling in Ge pFET Junctions

Analysis of gate-induced drain leakage mechanisms in silicon-germanium channel pFET

Journal	Data powered by TypesetIEEE Transactions on Electron Devices
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	00189383
Open Access	No