Header menu link for other important links
X
An accuracy tunable non-boolean co-processor using coupled nano-oscillators
Published in Association for Computing Machinery
2017
Volume: 14
   
Issue: 1
Abstract
As we enter an era witnessing the closer end of Dennard scaling, where further reduction in power supplyvoltage to reduce power consumption becomes more challenging in conventional systems, a goal of developing a system capable of performing large computations with minimal area and power overheads needs more optimization aspects. A rigorous exploration of alternate computing techniques, which can mitigate the limitations of Complementary Metal-Oxide Semiconductor (CMOS) technology scaling and conventional Boolean systems, is imperative. Reflecting on these lines of thought, in this article we explore the potential of non-Boolean computing employing nano-oscillators for performing varied functions. We use a two coupled nano-oscillator as our basic computational model and propose an architecture for a non-Boolean coupled oscillator based co-processor capable of executing certain functions that are commonly used across a variety of approximate application domains. The proposed architecture includes an accuracy tunable knob, which can be tuned by the programmer at runtime. The functionality of the proposed co-processor is verified using a soft coupled oscillator model based on Kuramoto oscillators. The article also demonstrates how real-world applications such as Vector Quantization, Digit Recognition, Structural Health Monitoring, and the like, can be deployed on the proposed model. The proposed co-processor architecture is generic in nature and can be implemented using any of the existing modern day nano-oscillator technologies such as Resonant Body Transistors (RBTs), Spin-Torque Nano-Oscillators (STNOs), and Metal-Insulator Transition (MITs). In this article, we perform a validation of the proposed architecture using the HyperField Effect Transistor (FET) technology-based coupled oscillators, which provide improvements of up to 3.5?increase in clock speed and up to 10.75?and 14.12?reduction in area and power consumption, respectively, as compared to a conventional Boolean CMOS accelerator executing the same functions. © 2017 ACM.
About the journal
JournalData powered by TypesetACM Journal on Emerging Technologies in Computing Systems
PublisherData powered by TypesetAssociation for Computing Machinery
ISSN15504832
Open AccessNo
Concepts (20)
  •  related image
    Architecture
  •  related image
    Cmos integrated circuits
  •  related image
    COPROCESSOR
  •  related image
    Electric power utilization
  •  related image
    Metal insulator boundaries
  •  related image
    Metal insulator transition
  •  related image
    Metals
  •  related image
    Mos devices
  •  related image
    Oscillators (mechanical)
  •  related image
    Oxide semiconductors
  •  related image
    Semiconductor insulator boundaries
  •  related image
    Structural health monitoring
  •  related image
    Transistors
  •  related image
    Vector quantization
  •  related image
    Coupled oscillators
  •  related image
    Digit recognition
  •  related image
    KURAMOTO
  •  related image
    MICRO ARCHITECTURES
  •  related image
    NON-BOOLEAN COMPUTING
  •  related image
    Computer architecture