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A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
Published in Institute of Electrical and Electronics Engineers Inc.
2007
Abstract
Process variation is an increasingly dominant phenomenon affecting both power and performance in sub-100 nm technologies. Cost considerations often do not permit overdesigning the power supply infrastructure for test mode, considering the worst-case scenario. Test application must not overexercise the power supply grids, lest the tests will damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. We argue that false delay test failures can be avoided by generating "safe" patterns that are tolerant to on-chip variations. A statistical framework for power-safe pattern generation is proposed, which uses process variation information, power grid topology and regional constraints on switching activity. Experimental results are provided on benchmark circuits to demonstrate the effectiveness of the framework. © 2007 IEEE.
About the journal
JournalData powered by TypesetProceedings - International Test Conference
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN10893539
Open AccessNo
Concepts (11)
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    COST ACCOUNTING
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    Electric power systems
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    Optimization
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    Program debugging
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    Random processes
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    Switching
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    DELAY TEST FAILURE
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    POWER GRID TOPOLOGY
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    POWER SUPPLY INFRASTRUCTURE
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    STOCHASTIC PATTERN GENERATION
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    Nanotechnology