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A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
, Nandwana R.K., , Kim S.-J., Talegaonkar M., Elkholy A., Choi W.-S., Elshazly A., Hanumolu P.K.
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 50
Issue: 4
Pages: 882 - 895
A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of -225.8 dB. © 1966-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Journal of Solid-State Circuits
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo