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A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata
Published in Institute of Electrical and Electronics Engineers Inc.
2015
Volume: 23
   
Issue: 10
Pages: 2352 - 2356
Abstract
In this brief, we consider quantum-dot cellular automata (QCA) realization of the discrete Hadamard transform (DHT). An analysis of a full-parallel solution based on efficient multibit addition in QCA is first presented. We show that this leads to large area as well as delay. We then propose a bit-serial pipelined architecture for QCA-based DHT. The proposed architecture is based on a new one-bit adder-subtractor requiring only six majority gates and a feedback latch that requires only one majority gate and limited wiring. The approach leads to a reduction in area-delay-cycle product of 74% and 91% (over a full-parallel solution) for wordlengths of 4 and 8, respectively. Results of simulations in QCADesigner are also presented. © 2014 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Very Large Scale Integration (VLSI) Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN10638210
Open AccessNo
Concepts (14)
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    Adders
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    Architecture
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    Cellular automata
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    Hadamard transforms
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    Pipeline processing systems
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    DISCRETE HADAMARD TRANSFORM
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    MAJORITY GATES
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    PARALLEL SOLUTIONS
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    Pipelined architecture
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    Proposed architectures
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    QCADESIGNER
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    QUANTUM-DOT CELLULAR AUTOMATA
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    Reduction in area
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    Semiconductor quantum dots