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A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converterPublished in Institute of Electrical and Electronics Engineers Inc.
2014
A phase interpolator (PI) based fractional divider is used to improve the quantization noise shaping properties of a 1-bit ΔΣ frequency-to-digital converter (FDC). Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed FDC in place of a high resolution TDC and achieves-102dBc/Hz in-band phase noise and 852fsrms integrated jitter (1k-40M) while generating 5.054GHz output from 31.25MHz input. © 2014 IEEE.
Topics: Phase noise (56)%56% related to the paper, Delta-sigma modulation (56)%56% related to the paper, Phase-locked loop (55)%55% related to the paper and Jitter (54)%54% related to the paper
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| Journal | Data powered by TypesetIEEE Symposium on VLSI Circuits, Digest of Technical Papers |
|---|---|
| Publisher | Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc. |
| Open Access | No |
Authors (2)
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