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A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS
, Shu G., Nandwana R.K., Talegaonkar M., Elkholy A., , Kim S.J., Choi W.-S., Hanumolu P.K.
Published in IEEE
Volume: 2015-August
Pages: 352 - 353
A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10-12 while operating at 14Gb/s with 12dB channel loss. © 2015 JSAP.
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JournalData powered by TypesetIEEE Symposium on VLSI Circuits, Digest of Technical Papers
PublisherData powered by TypesetIEEE
Open AccessNo