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A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth
Published in Institute of Electrical and Electronics Engineers Inc.
2019
Volume: 2019-June
   
Pages: C226 - C227
Abstract
We present a CTΔ Σ M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the reference path. 1/ f noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB. © 2019 JSAP.
About the journal
JournalData powered by TypesetIEEE Symposium on VLSI Circuits, Digest of Technical Papers
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo
Concepts (10)
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    Bandwidth
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    MODULATORS
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    Operational amplifiers
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    CLOCK-JITTER
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    FIR FEEDBACKS
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    LOW DISTORTION
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    Parasitic resistances
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    REFERENCE PATH
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    SWITCHED RESISTORS
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    Vlsi circuits