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A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC
, Baluni A.
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 2020-March
We present a single-bit continuous-time delta-sigma ADC that achieves 82.1 dB peak SNDR and 101.2 dB SFDR in a 65 nm CMOS process. The modulator, which operates with a sampling rate of 2.56 GHz, uses a 2x time-interleaved single-bit ADC in the loop. The key technique that enables low distortion is the use of a virtual-ground-switched resistive FIR feedback DAC, which operates in a 4x time-interleaved manner to reduce power dissipation. Interleaving artifacts, caused by mismatch, are addressed by mixed-signal calibration. The decimator is realized using polyphase techniques. The modulator and decimator consume 11.4mW and 15mW from a 1.1 V supply respectively. The Schreier FoM is 174.1 dB. © 2020 IEEE.
About the journal
JournalData powered by TypesetProceedings of the Custom Integrated Circuits Conference
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo