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A 14 nm 1.1 Mb embedded DRAM macro with 1 ns access
, Fredeman G., Plass D.W., , Reyer K., Knips T.J., Miller T., Gerhard E.L., Kannambadi D., Paone C.Show More
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 51
Issue: 1
Pages: 230 - 239
A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 m deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-AND-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 Mb macro composed of 8×2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor. © 2015 IEEE.
About the journal
JournalData powered by TypesetIEEE Journal of Solid-State Circuits
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo