We describe a low power analog front-end for a digital hearing aid, designed and fabricated in a 0.13μm CMOS process. The IC accepts inputs from a microphone or telecoil, amplifies and digitizes it for processing by a DSP, accepts digital data from the DSP, converts it to analog form using a pulse width modulated class D amplifier, and drives the earpiece, all over a 10kHz bandwidth. The programmable gain amplifier uses current sharing in the input stage to obtain low noise with low power consumption. The single-bit continuous-time ΔΣ ADC and the closed loop class-D amplifier use assisted opamp integrators to reduce power dissipation. An on chip ring oscillator provides the clock to the digital parts of the chip and to the digital signal processor (DSP). The chip has an input referred noise of 2.1μV, a dynamic range of 106 dB, an output THD of 0.006% and a peak output SNR of 79dB. It occupies 2.3 mm2 and consumes 285μA from a 1.2V supply. © 2013 IEEE.