The high dynamic range of CTΔΣMs used in wireless receivers, needed to accommodate large out-of-band interferers, can be reduced by using a filter up front. Embedding the filter inside the modulator loop is more power efficient. Prior work has embedded a Tow-Thomas biquad inside the ADC. We show that using a Rauch filter instead yields higher out-of-band linearity (for the same power dissipation) due to the passive-RC filtering inherent in the Rauch structure. The theory is borne out by measurements from a 1 MHz bandwidth CTΔΣM with an embedded second-order Rauch filter, achieving 76 dB SNDR and 36 dBFS out-of-band IIP3 while consuming 2.2 mW in a 65 nm CMOS process1. © 2018 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

Saravana Manivannan

Analog to digital conversion

Bandwidth

Continuous time systems

CMOS processs

Continuous-time

DELTA-SIGMA ADC

High dynamic range

POWER EFFICIENT

RC-FILTERING

Second orders

WIRELESS RECEIVERS

Passive filters

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IIT Madras

A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP 3 and 76 dB SNDR

2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT Δ Σ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given. © 2019 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

Conventional continuous-time delta-sigma modulator (CTDSM) architectures do not allow independent control of the shape and bandwidth of the signal transfer function (STF), since the STF is simply a by-product of NTF synthesis. This is particularly troublesome when the input to the CTDSM consists of large out-of-band interferers; handling them without saturating the quantizer needs larger inband DR, leading to increased power dissipation. A solution to this problem is to use a filter upfront to attenuate interferers. Alternatively [1], the filter can be moved into the CTDSM loop. In [1], a 1st-order RC filter was used to 'tame' the STF peak of a cascade of integrators with feedforward summation (CIFF) DSM. Apart from the limited selectivity offered by a 1st-order filter, an active feedback path was necessary to stabilize the loop. The CTDSM in our work obtains an STF with a sharper transition band and a lower cutoff frequency (normalized to the desired signal bandwidth) compared to [1], with the aim of more effectively attenuating close-in interferers. This is realized by embedding a 2nd-order active filter into the CTDSM. We show that this has the same functionality as the filter upfront, but achieves better linearity (for the same noise and power dissipation) when compared to the filter-CTDSM cascade. Further, no extra active circuitry is necessary to stabilize the loop. Measurements of a CTDSM (signal BW=2MHz), with a built-in VGA (0 to 18dB) and a 2nd-order Butterworth filter (4MHz cutoff), show that the out-of-band IIP3 improves by about 10dB when compared to the CTDSM with the filter placed upfront. The filtering CTDSM+VGA, which uses a single-bit quantizer and a 4-tap FIR DAC, achieves a DR of 92dB in a 2MHz BW while consuming 5mW in a 0.13μm CMOS process. The peak instantaneous DR/SNR/SNDR are 82/80.5/74.5dB. With the VGA, the DR is 92dB. © 2014 IEEE.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A 5mW CT ?S ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW

Continuous-time ΔΣ modulators (CTDSM) used in wireless systems need to process signals in the presence of interferers. Peaking in the Signal Transfer Function of a conventional design necessitates a higher in-band dynamic range to accommodate interferers. A filter up front solves this problem at the expense of increased power dissipation and degraded linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. However, having the filter inside a ΔΣ loop can be problematic with respect to stability. We show that such a system can be stabilized in a robust manner without extra hardware. Measurements of a CTDSM (signal BW = 2 MHz), with a built-in VGA (0 to 18 dB) and a second order Butterworth filter (4 MHz cutoff), show that the in-band/out-of-band IIP3 improves by about 3/10 dB when compared to the filter-CTDSM cascade, and achieves a similar dynamic range and consumes 25% lower power. © 1966-2012 IEEE.

IEEE Journal of Solid-State Circuits

Design techniques for continuous-time ΔΣ modulators with embedded active filtering

2013 Proceedings of the ESSCIRC (ESSCIRC)

A 9MHz filtering ADC with additional 2nd-order &#x0394;&#x03A3; modulator noise suppression

2011 Proceedings of the ESSCIRC (ESSCIRC)

A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

A 4.7mW 89.5dB DR CT complex ΔΣ ADC with built-in LPF

A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR

Journal	Data powered by Typeset2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open Access	No