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80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexityPublished in Institute of Electrical and Electronics Engineers Inc.
2016
Volume: 2016-September
An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (∼30%) to satisfy 10 year retention at 105° C. © 2016 IEEE.
Topics: Programmable logic array (61)%61% related to the paper, Pass transistor logic (57)%57% related to the paper and Logic family (56)%56% related to the paper
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About the journal
| Journal | Data powered by TypesetIEEE Symposium on VLSI Circuits, Digest of Technical Papers |
|---|---|
| Publisher | Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc. |
| Open Access | No |
Authors (3)
Janakiraman Viraraghavan- 80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory with No Added Process Complexity
- A 14 nm 1.1 Mb embedded DRAM macro with 1 ns access
- 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
- Statistical compact model extraction: A neural network approach
Guhan Jayaraman- Online performance monitoring of recombinant protein production in a fed-batch reactor
- Transcription analysis of hyaluronan biosynthesis genes in Streptococcus zooepidemicus and metabolically engineered Lactococcus lactis
- Recombinant protein purification using gradient assisted simulated moving bed hydrophobic interaction chromatography. Part II: Process design and experimental validation
- Design of aqueous two-phase systems for purification of hyaluronic acid produced by metabolically engineered Lactococcus lactis
