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32nm general purpose bulk CMOS technology for high performance applications at low voltage
, Arnaud F., Liu J., Lee Y.M., Lim K.Y., Kohler S., Chen J., Moon B.K., Lai C.W., Lipinski M.Show More
Published in IEEE
This paper presents for the first time a full 32nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (Avt∼2.8mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent Static Noise Margin (SNM) of 213mV has been achieved at low voltage for a high density 0.157um2 SRAM cell. Hierarchical BEOL based on Extreme Low k (ELK) dielectric (k∼2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125°C.
About the journal
JournalData powered by TypesetTechnical Digest - International Electron Devices Meeting, IEDM
PublisherData powered by TypesetIEEE
Open AccessNo
Authors (3)